Texas Instruments has experienced many "tribulations" in mixed analog and digital design, according to Chris Collins, director of TI's Analog Division. But significant progress is underway. At a keynote speech at the recent Mixed-Signal Technology Summit held at Cadence Sept. 20, Collins described a scalable, top-down, mixed-signal design and verification flow that is resulting in an "off the charts" first-pass silicon success rate.
The Mixed-Signal Technology Summit also included opening remarks by Chi-Ping Hsu, senior vice president, Cadence; an academic keynote by Prof. Ali Niknejad, University of California at Berkeley; presentations from Cadence R&D experts, customers, and partners; and a closing panel discussion that included several customer representatives. You can find a preview here.
Chris Collins of TI speaks at the Mixed-Signal Technology Summit
In his talk, Collins provided a brief history of mixed-signal design and EDA tool development at TI. He talked about the mixed-signal challenges that designers struggle with every day, discussed existing design and verification flows, and highlighted the new, scalable mixed-signal flow that TI is developing in collaboration with Cadence. He also offered a look at the future of mixed-signal design at TI.
An 80-year History
I won't try and summarize the history of innovation that Collins described at TI, but here are a few points that stood out:
- TI started in the 1930's and has been a mixed-signal company for over 80 years
- TI developed its own EDA tools until the 1990s, starting with an automated design-rule checking (DRC) tool called Ver in the 1970s - which is still in use today
- The company has spent nearly $9 billion in mixed-signal R&D over the past 5 years
- TI has some 80,000 products, and the Analog Division puts out over 800 chips per year
In the 1990s, Collins observed, the EDA industry focused on digital design, resulting in "what I call the dark ages of mixed-signal" until around 2005. He acknowledged that Cadence has made a significant investment in mixed-signal R&D in the past 5 to 6 years (Chi-Ping Hsu noted a $50 million investment in his keynote). "Now there's much better balance, and I'm hopeful Cadence will move forward helping us continue this journey," he said.
Collins discussed how TI works with Cadence. He talked about meeting quarterly with Cadence account teams and leaders, and having "very candid conversations" about what's important to TI. He also participates in structured management reviews that have more of a long-range focus. Finally, TI has started to use a hosted VCAD (virtual CAD) chamber at Cadence, making it possible to replicate a tool setup without sending somebody to India or China.
Trials and Tribulations
Collins cited a number of lessons that TI has "learned the hard way" over the past 80 years. One lesson is that pure analog designers should stop doing digital design. "Analog designers are some of the most amazingly smart people I've ever met," he said. "They can pick up a book and figure out how to do something in 5 minutes. They're also not very organized and structured as a whole. We've had 2,000 gate designs that an analog designer has tried to design, and taken four months, while a digital designer could do it in two weeks."
Other "tribulations" include:
- Mixing signals between analog and digital partitions is problematic - interface elements should be "invisible"
- Languages and data type connection challenges are increasing, and negating simulation speed improvements
- Setup and debug time are becoming critical
- Having a plan, configuration management, and discipline is key
Collins went on to discuss three design styles at TI - small A/small D, big A/small D, and big A/big D. With the latter, he noted, Fast SPICE is problematic for digital designers, and analog designers lack proficiency with Verilog-AMS. "So we do it the way a lot of you do it - we do it separately," he said. "Then we tie them together the last week of tapeout and hope the part wiggles."
A Better Flow
Can a better design and verification flow overcome tribulations? Collins is hoping to accomplish that with MVC, a flow that TI is developing in collaboration with Cadence. MVC stands for MOTIF/VERSE/CoSim, three elements that need some explanation on their own:
- MOTIF (Mixed-Signal Oriented, Top-down Integration Flow) offers top-down schematic generation that feeds into the Cadence database. It has automatic wiring capabilities and input syntax checking.
- VERSE (Verification Event-based Real Number Simulation Environment) provides event-based, analog functional modeling and hierarchical netlist extraction. It uses Incisive Enterprise Simulator (formerly NSim) and a top-level validation flow, and offers pin-type matching checks.
- CoSim combines Cadence event-driven HDL simulation and SPICE, or UltraSim Fast SPICE, in a co-simulation environment.
MVC, Collins noted, scales from very small digital designs to huge mixed-signal designs that are going into multi-chip modules (MCMs). "It definitely reduces our release to production cycle time," he said, noting that first pass success is much higher in TI groups that use MVC.
Still, future mixed-signal design challenges remain. Collins said that bottom-up design and verification techniques will fall short; digital content will increase; analog customization will leverage embedded software, requiring a knowledge of firmware; multiple ICs will be packaged together; testability of complex analog designs is getting harder; device characterization is more complex; and schedules are getting shorter.
To help solve these problems TI is working on SLICE, a system-level interface program for IC integration; ADEPT, advanced die/package integration; and AMSmadeEZ, a project intended to simplify setup for analog/mixed-signal engineers. TI is also working on behavioral model generation, universal test flows, persistent testbenches, and a unified lab characterization methodology. The overall message is "Mission is Possible" - yes, it is possible to align analog, digital, and RF domains, if engineers have the right tools and skills.
Richard Goering