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SKILL for the Skilled: Many Ways to Sum a List (Part 1)
A while back I presented a one day SKILL++ seminar to a group of beginner and advanced SKILL programmers. One example I showed was Variations on how to sum a list of numbers. This is a good example...
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Things You Didn't Know About Virtuoso: The (Setup) State of Things
Apologies for the long delay between articles (best intentions and all that). I last left you with an article about how to parameterize and manipulate device properties in your design without having...
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Mixed-Signal Methodology Guide Authors Speak Out
Cadence recently published the Mixed-Signal Methodology Guide, a first-of-its-kind book that offers a comprehensive review of the design, verification and implementation techniques required for today's...
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Digital Logic in Analog Block – How Will You Test It?
Analog IP blocks these days have increasing amounts of digital control logic. With very small amounts of digital logic, it's possible to just draw gates on the schematic and run targeted tests that...
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Simple Steps to Debug DRC Violations Undetected in EDI System
You've placed and routed your design in the Encounter Digital Implementation (EDI) System. It passed Verify Geometry and Verify Connectivity without a violation. Great!But when you run DRC signoff with...
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SKILL for the Skilled: Many Ways to Sum a List (Part 2)
In the previous posting, SKILL for the Skilled: Many Ways to Sum a List (Part 1), I showed a couple of ways to arithmetically sum up a given list of numbers. In particular, I presenting the following...
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What's Good About ADW’s Flow Manager? Check out the 16.5 Release and See!
The 16.5 Allegro Design Workbench (ADW) Flow Manager has been enhanced to provide a more flexible and robust designer experience. It can now be launched in a stand-alone mode, is faster in launching,...
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Lessons for EDA When Low Power vs. Heat Dissipation Isn’t a Fair Fight: A...
Right up there with functional verification, the challenges of low power design and verification present an existential threat to our customers' products, and ultimately their businesses. Clearly both...
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Free UVM Tutorial Boosts IC Functional Verification Skills
Whether you're new to the Universal Verification Methodology (UVM) or an experienced user who wants to know more, a free on-line tutorial will help you improve your IC verification skills. The half-day...
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Accelerated VIP Delivers Value for Firmware/Driver Validation and Integration
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iPhone5 Differentiation is Chip Design
In case you may have missed it, Apple recently launched a new iPhone. As per the iPhone launch tradition, it brings with it a lot of excitement over the latest capabilities. Of course we don't know...
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MemCon Keynote: Why Hybrid Memory Cube Will “Revolutionize” System Memory
DDR3 and DDR4 aren't enough - it's time for a "revolution" in system memory that will offer exponential improvements in bandwidth, latency, and power efficiency, according to Scott Graham (right),...
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Speed of “Light” – My First iPhone 5 Impression
So what’s the big deal with the iPhone 5? Some folks have commented: "It is just a bit faster, taller, lighter – no big deal." Let me tell you one thing: Seeing, no handling and touching is believing....
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Free Low Power Summit – Dr. Jan Rabaey, ARM, Freescale, and More
If you're involved - or just interested - in any aspect of low-power electronics design, you'll find a lot of good information at a one-day Low-Power Technology Summit at Cadence headquarters in San...
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Shameless Promotion: Free Club Formal San Jose (with Lunch) on Wednesday 10/17
Please join Team Verify and other design and verification engineers at the next "Club Formal" on the Cadence San Jose campus on Wednesday, October 17 at 11:30am. This free, half-day event (including...
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Allegro 16.6: Easing PCB Design for Multi-Gigabit/Second Signals
Got a few picoseconds to spare? If you're a PCB designer working with a multi-Gbit/second serial link interface such as PCI Express 3.0 or a DDR memory interface, maybe not. Two new features in the...
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What's Good About Allegro PCB Editor PDF Publisher? See for Yourself in 16.5!
Starting with release 16.5, it is possible to export data from Allegro PCB Editor into PDF files. PDF files are more portable and secure in comparison to .brd files and can be used by customers to...
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ARM-Based Microcontrollers using Cadence’s Mixed-Signal Solution
I recently came across a Wall Street Journal article,"ARM Chases Bigger Slice of Smaller Chips," that provides a very interesting perspective on how ARM is positioned to capture the microcontroller...
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MemCon Panelists Chart Future of Semiconductor Memory
Density, power, bandwidth, latency - all of these memory attributes will improve during the next few years, according to panelists at the MemCon 2012 conference Sept. 18. But don't underestimate the...
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Keynote: From “Tribulations” to Mixed-Signal Success at Texas Instruments
Texas Instruments has experienced many "tribulations" in mixed analog and digital design, according to Chris Collins, director of TI's Analog Division. But significant progress is underway. At a...
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