Being an intern at Cadence was a rewarding and impactful experience that kickstarted my career. I got a firsthand view of life in Silicon Valley working with a tech company. Being an intern at a FORTUNE 100 Best Companies to Work For® came with t...(read more)![]()
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Interns Making an Impact
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Ford: Automotive OEM to Software Manufacturer?
Soon after Marc Andreesen founded the venture capital firm Andreesen-Horowitz (a16z) ten years ago, he wrote a piece, Why Software Is Eating the World, that the WSJ published in 2011. I happened to hear the latest a16z podcast this morning, Software ...(read more)![]()
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IC Packagers: Rule Your Package Designs
When it comes to package design, spacing often reigns supreme. The location readout in the bottom status bar of the tool will always tell you where your cursor is in the design; this can show either absolute or relative mode (in which case coordinate...(read more)![]()
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Now Access COS Directly from the Tool interface
As designs become complex and performance targets increase, time shrinks. Designers need to minimize time setting up design flows or trying to find workaround for many issues that might occur during tape out. Cadence Online Support Portal (COS) ensures 24x7 technical assistance to quickly address your technical issues and queries.
In our continuous effort to improve the usability of COS portal and efficiency of its usage, we are introducing COSLite to provide access to the relevant and curated content from the tool interface (starting with 19.11 releases of Innovus, Tempus, Voltus, and Genus). The COSlite can now be easily accessed by running the tool in the GUI mode through the Help pulldown menu.
For more details and FAQs, click here.
We hope you will enjoy using COSLite to troubleshoot your issues quickly and seamlessly.
-Mukesh Jaiswal
Sr. Knowledge Manager (Digital and Sign-off Solutions)
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CDNLive China 2019
A couple of weeks ago it was CDNLive China in Shanghai. (To read about how I got into town from Shanghai Pudong Airport, see my post Maglev Trains.) Once again, I was giving away copies of A Year of Breakfasts 2018 and signing people up for Sunday Br...(read more)![]()
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Spectre Xplored - The New Spectre X Simulator
The new release of the Spectre® X Simulator (Spectre 19.1) enables large-scale verification simulation for complex analog, RF, and mixed-signal blocks and subsystems, while maintaining the golden accuracy expected of the Spectre simulation family. The new Spectre Xplored blog series will include posts on new features in the Spectre X Simulator platform and tips on how to use them. Stay tuned for more to come!
For a while now, the electronic design community has been missing a key piece of technology to handle the ever-expanding size of analog and RF ICs and systems. Traditional SPICE simulators, normally used to ensure accuracy, were having trouble simulating the massive increases in both devices and post-layout parasitics. In addition, they were deficient in handling the new architectures that were becoming more popular. Even though traditional FastSPICE simulators could handle the new capacity needs, unfortunately, their accuracy level was not acceptable to analog designers.
Cadence® recently introduced the new Spectre® X Simulator, which is an ideal solution for these design problems. The new Spectre X Simulator is specifically geared for simulation of massive amounts of data paired with the high level of accuracy designers expect.
Based on the same golden Spectre accuracy customers have experienced for over 30 years, the Spectre X Simulator is a massively parallel circuit simulator that delivers 3X to 10X performance gains and can solve 5X larger designs, enabling designers to effectively simulate circuits containing millions of transistors and billions of parasitics in a post-layout verification flow.
The Spectre X Simulator includes internal optimization techniques for device modeling and post-layout simulation. It also leverages modern compute hardware to perform scalable, massively distributed simulations that reduce simulation time from days to hours.
With the new abilities provided by the Spectre X Simulator, engineers can now analyze designs that previously could only be estimated through abstractions, circuit partitioning, extreme parasitic reductions, and hope! In addition, with numerous endorsements from customers verifying the performance gain and accuracy, the Spectre X Simulator is uniquely equipped to handle the challenges of verifying the performance of circuits for emerging designs.
Related Information
- Spectre 19.1 Release Now Available
- Tales from DAC: The New Spectre Simulator Is Here!
- Tales from DAC: MediaTek's Experience with Spectre X Simulator
- Spectre X: Same Accuracy, New Speed
About Spectre Xplored Blog Series
The Spectre X Simulator (Spectre 19.1) enables large-scale verification simulation for complex analog, RF, and mixed-signal blocks and subsystems, while maintaining the golden accuracy expected of the Spectre simulation family. The Spectre X Simulator can perform massively distributed simulation workloads for greater speed and capacity. Paired with our comprehensive Custom IC solution portfolio, we can provide the most interoperable flow across chip, package, module and board in the industry.
The Spectre Xplored blog series includes posts on tips and features of the new Spectre X Simulator. Enter your email address in the Subscription box at the top of the page to receive notifications about our Spectre Xplored posts.
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The Cadence Academic Network
Just a few weeks ago, I attended a workshop that many Cadence employees were encouraged to take. My group was a nice cross-section of about twenty people across organizations at Cadence, and it was great to interface with people outside of my organiz...(read more)![]()
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BoardSurfers: PCB Design Technique for Designing a Small RF Section in a Digital Board
Are you designing a 5G or radar application, or for that matter any application, that requires RF components? Are cost, size-reduction, and performance improvement major concerns for you? Most probably they are. Here we talk about an innovative solution for mixed-signal RF designs using Cadence layout editors.(read more)![]()
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Ken的博客系列之四 | 千兆位串行链路接口的SI方法
作者：Ken Willis
上一篇：IBIS-AMI建模启用约束驱动设计
通过构建预布局测试平台，填入相关模型，生成结果逼真的仿真结果，这时候正适合启用约束来驱动和控制串行链路的物理布局。这可能会导致测试平台需要一些改进和迭代，来添加更多的细节，这是可预期的。此时的方法是参数化测试平台的关键元素，扫描它们以量化其对整个接口性能的影响，并限制那些参数以确保我们的设计在完成时满足合规要求。在PCI Express Gen 4的情况下，核心要求是眼图高度至少为15mV，眼图宽度为0.3UI（对于16...(read more)![]()
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CDNLive India 2019: And The Best Paper Award Goes To...
What a whirlwind of two months it has been! And it has been totally worth it, with CDNLive India featuring a huge number of customers, fantastic user-authored presentations and insightful keynotes.
A more detailed review will follow, but here is the ...(read more)![]()
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Virtuosity: Automated Device Placement and Routing—Row-based Device Placement
This blog, the third one in the Automated Device-Level Placement and Routing series, highlights the importance of following a gridded methodology for placement and routing. You'll see how the automated device-level layout flow lets you derive WSPs and row regions automatically, based on the device footprint, layers, and DRCs, with minimal user input.(read more)![]()
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Labor Day Off-Topic: Have You Been to Suomi?
If you've been in the semiconductor, electronics, or mobile business for some time, chances are that you have been to Suomi. At one point it was the leader in mobile phone handsets. You just might not have realized it. It is the Finnish name for ...(read more)![]()
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Interns Making an Impact
Being an intern at Cadence was a rewarding and impactful experience that kickstarted my career. I got a firsthand view of life in Silicon Valley working with a tech company. Being an intern at a FORTUNE 100 Best Companies to Work For® came with ...(read more)![]()
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Girls Who Code Reflect on Their Summer at Cadence!
This summer, 21 tenth- and eleventh-grade girls came to Cadence’s San Jose campus as part of our partnership with Girls Who Code. The Summer Immersion Program lasted seven weeks and provided the girls with a no-cost curriculum introducing them...(read more)![]()
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Sunday Brunch Video for 1st September 2019
https://youtu.be/_DiWWBDQbGc
Made at CDNLive India (camera Corrie Callenbach)
Monday: HOT CHIPS: Chipletifying DesignsTuesday: Ford: Automotive OEM to Software Manufacturer?
Wednesday: CDNLive China 2019
Thursday: HOT CHIPS: Intel InsideFriday...(read more)![]()
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Virtuosity: Device-Level Routing for Advanced Nodes – Trunk-to-Trunk Mesh Routing
This blog highlights the importance of trunk-to-trunk mesh routing feature for providing customized device-level routing solutions and how it helps layout designers to be more efficient and organized.(read more)![]()
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HOT CHIPS: The Tesla Full Self-Driving Computer
On April 22, Tesla held its Autonomy Day. They announced their "Self-Driving Computer" or SDC. (You can read my post from back then in my post Tesla Drives into Chip Design.) I have said several times over the years that I expected that t...(read more)![]()
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IC Packagers: Manufacturing Cross-Hatched Shapes
If you use cross-hatched shapes in your package design, you are doubtless aware of some considerations. Namely, if your shape outline is anything but a rectangular outline at a multiple of the hatch line width pattern, and unless it has no objects to...(read more)![]()
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BoardSurfers: PCB Electronics - Component Placement - Get Set and Go!
How do you place components on a PCB design? Manually? Or quickly using automation? Is there a way to rotate or mirror components while placing them? Is there a way to determine the congested areas or the flow within blocks even while placing components? How do you ensure the placed components are aligned? How o you verify all is well with the board? Read on for the answers.(read more)![]()
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Conformal Litmus
One of the earliest science experiments I can remember doing was crushing red cabbage in a mortar and pestle with some sort of alcohol. The resulting purple liquid would turn red in acid and blue in alkali. True litmus is not extracted from red cabba...(read more)![]()
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