CDNLive Israel is coming up later this month on September 18 at the David Intercontinental in Tel Aviv. I will be attending as usual so you can expect some Breakfast Bytes posts later in the month.
1. A Day Dedicated to Your Interests
As al...(read more)![]()
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Ten Reasons to Attend CDNLive Israel
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Cadence and the Academic Network Support Design Contests in the Asia Pacific
Design contests are a unique way for students to get hands-on experience using Cadence® tools, while in a fun and competitive environment. It is important to the Cadence Academic Network to support design contests so that we can help the nex...(read more)![]()
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Virtuosity: Support for Stacked Devices in Modgen
This blog provides an overview of the support for stacked devices in Modgen. This feature makes it easy for you to visualize and edit devices in highly-complex designs, which, in turn, helps achieve higher circuit performance goals in advanced node PDKs. Read the blog post to know more about how to work with stacked devices in Modgen.(read more)![]()
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CDNLive India 2019: Mediatek and More
If you live in California, as I do, then India is a long way away. It is 11½ hours time difference, for a start. Air India has a direct flight from San Francisco to New Delhi (over 16 hours) but since CDNLive is in Bangalore, that is not ...(read more)![]()
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Ken的博客系列之五 | 千兆位串行链路接口的SI方法
作者：Ken Willis
上一篇：启用约束驱动设计高效的互连提取
一旦物理layout完成（或者至少串行链路差分对的布线完成），就可以进行布局后验证。需要决定使用多大的带宽进行模型提取。为了评估这一点，需要考虑通过链路传递的信号。 PCI Express Gen 4的规格是指上升时间约为22ps，测量值为10%至90%。将上升时间与信号带宽相关联的经典表达式是：
BW (GHz) =350 / Trise (ps)
对于PCI Express Gen 4来说，我们首先考虑的是至少16 GHz...(read more)![]()
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Sunday Brunch Video for 8th September 2019
https://youtu.be/AvimlRMDZng
Made at Cadence parking lot (camera Steve Brown)
Monday: Labor Day
Tuesday: HOT CHIPS: The Tesla Full Self-Driving Computer
Wednesday: Conformal Litmus
Thursday: Ten Reasons to Attend CDNLive IsraelFriday: CDNL...(read more)![]()
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Dimensions to verifying a USB4 design
Verification of a USB4 router design is not just about USB4 but also about the inclusion of the three other major protocols namely, USB3, DisplayPort (DP) and PCI Express (PCIe). These protocols can be simultaneously tunneled through a USB4 router. Put in simple terms, such tunneling involves the conversion of the respective native USB3, DP or PCIe protocol traffic into the USB4 transport layer packets, which are tunneled through a USB4 fabric, and converted back into the respective original native protocol traffic.
It may sound simple but is perhaps not.
There are several aspects in a router that come into picture to carry out this task of conversion of native protocol traffic, route it to the intended destination, and then convert it back to the original form. Some of those are the USB3, DP and PCIe protocol adapters, transport mechanism using routing, flow control, paths, path set-up and teardown, control and configuration, configuration spaces.
That is not all. There are core USB4 specific logical layer intricacies as well, which carry out the tasks of ensuring that all the USB4 ports and links are working as desired to provide up to 40Gbps speed and that the USB4 traffic flows through out the fabric in the intended way. These bring on the table features like High Speed link, ordered sets, lane initialization, lane adapter state machine, low power, lane bonding, RS-FEC, side band channel, sleep and wake, error checking.
All of these put together give rise to a very large verification space against which a USB4 router design should be verified. If we were to break down this space it can be broadly put in the following major dimensions,
- Protocol Adapter Layer
- USB3 tunneling
- DP tunneling
- PCIe tunneling
- Host Interface Adapter Layer
- Transport Layer
- Flow control
- Routing
- Paths
- Configuration layer and control packet protocol
- Configuration spaces
- Logical Layer
The independent verification of these dimensions is not all that would qualify the design as verified. They have to be verified in various combinations of each other too. Overall, all the parts of a USB4 router system need to be working together coherently.
For ex., the following diagram depicts the various layers that a USB4 router may comprise of,
A USB4 router or a domain of routers does not work on its own. There is a Connection Manager per domain, which is a software-based entity managing a domain. A router provides the various capabilities for a Connection Manager to carry out its responsibilities of managing a domain.
It would not be an exaggeration to say that the spectrum of verification of a USB4 router ranges from the very minute details of logical layer to the system-level like multiple dependencies as the whole USB4 system is brought up layer by layer, step-by-step.
Cadence has a mature Verification IP solution that can help in the verification of USB4 designs. Cadence has taken an active part in the working group that defined the USB4 specification and has created a comprehensive Verification IP that is being used by multiple members in the last two years.
If you plan to have a USB4 compatible design, you can reduce the risk of adopting a new technology by using our proven and mature USB4 Verification IP. Please contact your Cadence local account team for more details and to get connected.
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HOT CHIPS: In-DRAM Compute
Something that has been discussed for years is the fact that we could add processors to DRAM memory pretty cheaply if we could work out what to do with them. Usually, when people suggest this, they don't really think it through. They are assuming...(read more)![]()
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Virtuoso Meets Maxwell: Add Some MAGic to Your ElectroMAGnetic Analysis
If you’ve ever seen a great magician at work, you know that their talent lies in making the impossible look easy. That’s what we have done with Electromagnetic (EM) Analysis in the Virtuoso RF Solution. If you have struggled with cumbersome EM integrations in the past, read further to know what new we have in store for you.(read more)![]()
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CDNLive India 2019: NXP and More
Last week I covered Day 1 of CDNLive India. Today it is the turn of verification and PCB/system. With a digression to India's unusual time zone.
Day 2
On Thursday, August 29, there were tracks for Advanced Verification Methodology, Performan...(read more)![]()
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Virtuoso IC6.1.8 ISR6 and ICADVM18.1 ISR6 Now Available
The IC6.1.8 ISR6 and ICADVM18.1 ISR6 production releases are now available for download. (read more)![]()
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BoardSurfers: PCB Electronics - Electrical Constraints
Whether it's NASA's space missions or a school camping trip; building a cutting-edge, reusable rocket system or baking a simple lemon tart - planning is a must to avoid disasters, or at least to get a predictable output. So is the case with PCBs. You want to plan ahead to avoid design mistakes that can cost you money and time. And that's where constraints come handy.(read more)![]()
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IC Packagers: How Far Away are You?
Layout design is all about clearances. Daily challenges come from maintaining consistent space between your differential pair members, calculating the number of routing channels you can squeeze between two vias, or ensuring adequate clearance of bond...(read more)![]()
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How to Land a Job at Cadence: Recruiters Share Their Best Tips for Standing Out and Getting an Interview
As we send off the last of our 2019 Summer Interns (read more about their experience here) and say goodbye to summer, our recruiting team is already turning their attention to finding the next group of college hires and interns to join the Cadence te...(read more)![]()
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EDPS Preview 2019
EDPS, the Electronic Design Process Symposium, is coming up next Monday. It will be on Thursday, October 3 and Friday, October 4. Once again it will be held at SEMI's offices in Milpitas. I think of it as Gary Smith's conference, since h...(read more)![]()
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Safety and Aging in IoT Devices: What We Know Today
How do we achieve highly accurate aging data models for critical circuits in automotive or IoT applications?
IoT device aging isn’t well understood yet, since most of it is still so new. How will the software stand up against tomorrow’s t...(read more)![]()
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Intelligent Systems
Cadence's goal is to empower engineers at semiconductor and systems companies to create innovative, intelligent and highly differentiated electronic products that transform the way people live, work, and play. One big change is for system compani...(read more)![]()
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Intelligent System Design
Yesterday in my post Intelligent Systems, I wrote about how the imperative for differentiated products, especially at the high end of markets, is pushing both system and semiconductor companies to take a more holistic view of system design. Cadence c...(read more)![]()
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Ken的博客系列之六 | 千兆位串行链路接口的SI方法
作者：Ken Willis
上一篇：高效的互连提取使用IBIS-AMI模型进行仿真
此时，SerDes元器件供应商应该已经提供了所需的IBIS-AMI模型，如果这些模型可用，那么替换仿真测试平台中的对应模型。现在，我们重点关注后仿真的验证工作。在仿真测试平台中替换为你自己的模型，尽管这时看起来你好像就马上可以进行仿真工作了，但是对于IBIS-AMI模型仍然有许多工作需要做。
如前所述，算法部分或者IBIS-AMI模型的“AMI”部分为SerDes的均衡功能。在双沿数据速...(read more)![]()
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Sunday Brunch Video for 15th September 2019
https://youtu.be/bcAO52jxk10
Made at SFO (camera Carey Guo)
Monday: HOT CHIPS: In-DRAM ComputeTuesday: CDNLive India 2019: NXP and More
Wednesday: EDPS Preview 2019
Thursday: Intelligent SystemsFriday: Intelligent System Designwww.breakf...(read more)![]()
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